Embedded Software Development and Simulation of RISC-V Processors
If you are developing software for RISC-V ISA processors, systems using RISC-V devices, or RISC-V based cores, and where you do not have access to the hardware or you need a better embedded software development environment – then you probably need to have a look at using a simulator to develop your software on.
The key component in a RISC-V simulation environment used for developing embedded software is the RISC-V CPU model.
This site, risc-v-debug.com, with the title ‘Debugging software for RISC-V processor systems with Imperas tools’ and tagline ‘Using the Imperas debugger for developing RISC-V software’ provides information on the industry’s most comprehensive library of extremely fast and efficient CPU Models of RISC-V processor cores that work in a variety of simulation environments. The site, risc-v-debug.com, while focusing on Using the Imperas debugger for developing RISC-V software also provides information on the other Fast CPU Models available from vendors such as ARM, Imagination, MIPS, Renesas, etc. The whole focus of our RISC-V models is to enable you to develop embedded software in a more efficient way, with less bugs, and in less time.
“Imperas believes that the customizable, open RISC-V architecture is a boon to the embedded electronics industry, and that delivering our next-generation models, virtual platforms and software development methodology will help accelerate its adoption.” said Simon Davidmann, president and CEO of Imperas.
Rick O’Connor, Executive Director, RISC-V Foundation commented: “Imperas virtual platforms and models for the open RISC-V architecture will enable early software development, long before hardware is available. These RISC-V Imperas virtual platforms lower software development costs, increase quality, improve time to market, and reduce software development risks.”
Fast CPU Models of RISC-V ISA based processors, cores, and SoC
The RISC-V Fast Processor/CPU Models discussed in this site, risc-v-debug.com, ‘Debugging software for RISC-V processor systems with Imperas tools’, can be used in C, C++, or SystemC TLM based platforms which you can develop or you can use existing platform models (virtual platforms) available from several sources (e.g. OVP, Imperas). Readily available virtual platform models range from simple bare metal models through to full development board models such as the MIPS Malta or ARM Versatile Express which can run operating systerns like FreeRTOS and Linux.
All the models listed on this site, risc-v-debug.com, ‘Debugging software for RISC-V processor systems with Imperas tools’, have been developed in C using OVP technology and for SystemC TLM have been tested to run with all major SystemC simulators: Cadence, Synopsys, Mentor, and Accellera/OSCI. The models have also been tested with emulators from Synopsys ZeBu, Cadence Palladium, Mentor Veloce, and Aldec. The models run on both Windows and Linux host platforms. Native OVP simulators (using C platforms) are available from Imperas and OVP.
On this site, risc-v-debug.com, ‘Debugging software for RISC-V processor systems with Imperas tools’, and ‘Using the Imperas debugger for developing RISC-V software’, you will see the scope and variety of the RISC-V Fast CPU Models available and how easy they are to download and use in C or C++ simulations.
Many companies have downloaded these models and use them within their own internal simulation environments. There are specific APIs to easily allow simulator integration and encapsulation. Cadence working with Imperas is one example.
Largest CPU Model Library in the Industry
Each Fast Processor Model is written in C using the Open Virtual Platforms (OVP) standard public APIs. They include a dedicated native C++ SystemC TLM2 interface provided as source to enable understanding and easy usage. Not only is the specific SystemC TLM2 interface provided as source (click to preview an example), also, the full model is available as source. The models do require a simulator that implements the OVP APIs – such as OVPsim available from OVP, or commercial simulators from companies such as Imperas Software.
There is documentation that explains about the models in general (click to preview) and for each model there is a specific document (click to preview the document for the RISC-V RV64G model) that describes what is available in the model, for example its ports, nets, registers, modes, exceptions, and other configuration/parameter options. On the OVP website there is lot of information about each model (for example click to browse the available information on the RISC-V RV64G model).
An overview document (click to preview) explains, with the use of examples, how the models are configured and used in SystemC TLM2 platforms.
In a C or C++/SystemC TLM2 environment, the models are used directly, with no inefficient co-simulation. It is very simple to create homogeneous or heterogenous platforms of advanced processor core models. To see examples of platforms ranging from one to twenty-four cores and for platforms that boot full operating systems like Linux and Android, including SMP, visit the the examples and platforms available from the OVP platforms download area or video area.
Many models can be instanced in one platform, virtual platform or virtual system prototype – it is easy to build multi-core multi-processor platforms.
Faster Models means BUGS ARE FOUND SOONER
The models run fast, hundreds of millions of instructions per second (MIPS):
If you need maximum available simulation speed from the Fast CPU Models, then you need to find our more about QuantumLeap from Imperas. This uses the parallel resources of the host PC to accelerate your simulations.
For more information on QuantumLeap parallel simulation acceleration using host resources and to find out how to develop your embedded software at the fastest speeds in the industry, browse the Imperas information.
Industry Standard Debug and IDE for RISC-V software development using models
Each model listed on this site, risc-v-debug.com, ‘Using the Imperas debugger for developing RISC-V software’, supports standard debugging interfaces and can be connected using RSP to GDB, either standalone or within an Eclipse IDE environment. The models also connect to the advanced multi-core debugger available as part of the Imperas Advanced Multicore Software Development Kit product.
Easy to use – watch the video
To see a short video of a Fast CPU Model of a RISC-V running in a simple platform – and see other models and platforms from Imperas and OVP, including running FreeRTOS and booting Linux, click the image:
If you want to see other videos, OVP has a collection to view here.
At the top of this page are several menu picks that list the different families and enable access to the model specific information. The listed items on the right provide news related information.
To explore how easy it is to use these Fast CPU Models of RISC-V, look at the OVP starting page.
If you are looking for products to use to develop embedded software visit the Imperas Software website.
Currently available Fast Processor Model Families.