The Most Complete Collection of Fast Instruction Set Simulators for RISC-V in the Industry
If you are developing software for a RISC-V processor, core, or system where you do not have access to the hardware – then you probably need to have a look at using a simulator to develop your software on. Reasons for not having access to the hardware are many. The most common being that the hardware is not yet designed or built and if this is a new chip then the use of a software model or ISS to get the software development started is essential.
With modern instruction sets and processor architectures it is essential that the code you develop is cross compiled and executed on the correct instruction set. Use of host x86 execution only goes so far for modern embedded processors. Many current embedded processors have DSP instructions or specific architectural instructions that affect CPU operation and these just will not exist in a different host processor. Also maybe you have a binary library of say an ARM or MIPS audio or video codec. This will just not run on an x86 and requires you run it on the correct Instruction Set Architecture (ISA). So running your code on the correct ISA is becoming more and more important to get started with early embedded software development.
An Instruction Set Simulator, or ISS, is often the first simulation product used in an embedded software development project. An ISS allows the development and debug of code for the target architecture on an x86/x64 host PC with the minimum of setup and effort. It simply requires the cross compilation of your application and running the ISS with an argument to specify the name of the application object.
Where can a RISC-V ISS be used in embedded software development?
A RISC-V ISS can be used by many different developers in different software development roles. Used by application software engineers who need to create software binaries on the latest architectures but who do not need platform components – a RISC-V ISS can work with a standard debuggers and GUIs which makes it very easy to get started with full source code interactive debugging.
Middleware library developers can also use a RISC-V ISS when building software libraries for common functions, for example multimedia standards where they code at the assembly level and make extensive use of the processor data path – a debugger/GUI shows detailed assembly and all processor registers.
Test engineers can use a RISC-V ISS in a regression test environment as it can be used in batch/scripted environments as well as being used interactively.
A key component of a RISC-V ISS is the detailed RISC-V CPU models it uses
The Imperas ISS makes use of the Imperas OVP Fast Processor Model library providing access to almost 200 different instruction accurate embedded CPU model variants from the Imagination/MIPS 24Kc to the ARM Cortex-A72MPx4 quad core 64 bit processor, through to the RISC-V RV32G and RV64G. The Imperas ISS product package comes with all these CPU models and example usage of them.
This site, risc-v-debug.com, ‘Debugging software for RISC-V processor systems with Imperas tools’, ‘Using the Imperas debugger for developing RISC-V software’, lists the many Fast Processor Models that are availble for RISC-V and other processor families.
With a modern ISS, speeds of up to 1,000 MIPS can be expected on modern desktop PCs.
Features of the Imperas RISC-V Instruction Set Simulator (ISS)
The Imperas RISC-V ISS is a program executable that is released to run in x86 32 bit Windows/Linux and x64 64 bit Windows/Linux environments.
There are command line arguments that select which processor family and specific processor variant, and which cross compiled application binary are to run.
The RISC-V ISS implements semi-hosting so that if your C program makes calls to standard newlib functions such as fopen, printf etc, then you need to just compile up your main.c and load it. The RISC-V ISS semi-hosting intercepts these newlib calls and implements them directly on the host making your cross-compiled application interact directly with the host PC.
- includes the full library of all publicly released Imperas OVP Fast Processor Models
- includes a GDB debugger for each CPU family
- includes the Imperas Graphical User Interface (iGui) to provide full source code debug
- configurable trace subsystem to provide instruction and register tracing
- loads .elf file binaries directly
- allows one instance of a single or multi-core CPU with full memory construction
- uses built in semi-hosting to support library functions such as printf and fopen, and can access host native resources
- can be run interactively or in script/batch mode for regression testing
- includes Imperas Just-In-Time (JIT) Code Morphing high performance CPU simulator technology
- works with Eclipse/CDT GUI
The Imperas RISC-V Instruction Set Simulator (ISS) includes a GUI and debugger
An Example run of the Imperas Instruction Set Simulator (ISS)
Easy to use – watch a tutorial video (requires login)
To see a video tutorial of the use of the ISS, click the image:
If you want to see other videos, OVP has a collection to view here.
Currently available Fast Processor Model Families.